Why Quantum Tunneling Explains Semiconductor Leakage Currents—And Drives Modern Chip Design Constraints

量子隧穿为何解释半导体漏电流——并驱动现代芯片设计约束

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As transistor gate oxides shrink below 2 nm, electrons tunnel through classically forbidden barriers—a quantum phenomenon that dominates off-state leakage in FinFET and GAA architectures.
Tunneling current scales exponentially with barrier thickness: halving oxide width increases leakage by 10⁴×, forcing designers to trade switching speed against static power consumption.

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